### 1 CHAPTER 1 INTRODUCTION 1

1

CHAPTER 1

INTRODUCTION

1.1 Introduction

In the present scenario data converters are being used in almost all the application of

narrow band extraction from wideband sources and narrow band construction of

wideband signals is becoming more important. These functions require two basic

signal processing procedures: decimation and interpolation. If the required sample-rate

is an integer multiple of the existing one, it is adequate to oversample the input signal

with the help of an interpolation filter. Similarly, if the existing sample-rate is an integer

multiple of the one that is desired, then the process of decimation or down-sampling can

be commissioned. Decimation is used to reduce the sampling rate by passing a signal

through low pass or band pass filter. Interpolation is used to increase the sampling rate.

Hogenauer proposed a class of digital linear phase Finite Impulse Response (FIR) filters

for the decimation and interpolation, which require no multipliers (use limited storage),

making them a viable substitute in the conventional implementation for certain

applications. The CIC architecture can be used for both interpolation and decimation.

In the CIC filter design, the pass-band response and stop-band rejection characteristics

are managed by three-integer parameters, which are number of stages, the differential

delay and the number of bits in input/output register. Higher the number of stages,

higher will be the existing stop-band attenuation. CIC filter can also used in Software

Defined Radio (SDR) systems.

The CIC filters are multiplication free filters with limited storage requirements, which

make them ideal for the high speed data converters. Hogenauer presented an FIR

structure, which consists of cascaded integrator stages working at the higher sampling rate

and the same number of comb stages working at the low sampling rate. A number of

cascaded integrator comb pairs are chosen to meet the design requirements for

aliasing or imaging errors. Cascaded Integrator-Comb (CIC), or Hogenauer filters, are

multirate filters used for realizing large sample rate changes in digital systems. CIC filters

are multiplierless structures, consisting of only adders and delay elements which is a great

advantage when aiming at low power consumption. They are typically employed in

applications that have a large excess sample rate. That is, the system sample rate is much

larger than the bandwidth occupied by the signal. CIC filters are frequently used in Digital

Down-Converters (DDCs) and digital up-converters. Although, the CIC filters can

2

implement decimation and interpolation efficiently in the hardware for a wide range of

rate change factors, yet CIC filter response is lacking in a flat pass-band response

and better transition bandwidth. To circumvent these problems, a compensation FIR

filter can be employed in cascade with the CIC filter to provide frequency correction

as well as spectrum shaping.

1.2 Fundamental of digital filters

There are two basic types of digital filters, Finite Impulse Response (FIR) filters and

Infinite Impulse Response (IIR) filters. The general form of the digital filter transfer

function is given as

( )

Digital filters for which M ? 1 (and aM ? 0), are called IIR filters, because their impulse

response sequence has an infinite duration – it never dies out completely.

Fig.1.1: Direct realization of IIR filters

Digital filters for which M = 0, are called FIR filters, because the impulse response is

nonzero for a finite number of samples. FIR filters transfer function is given as

( ) =

3

Fig.1.2: Direct realization of FIR filters

1.3 FIR filters

FIR filters can be used for the process of decimation and are also known as non-recursive

filters. The output of FIR filter depends upon past and present values of input. The FIR

Decimation block resamples the discrete-time input at a rate K times slower than the input

sample rate. The block down samples the filtered data to a lower rate by discarding (K-1)

consecutive samples following every sample retained. The design of FIR filter is based on

the often added requirement that the phase response be linear. FIR filter is not based on

any feedback path and can easily be designed to be linear phase by making the coefficient

sequence symmetric i.e. equal delay at all frequencies. This property is sometimes desired

for phase-sensitive applications.

Limitations

The disadvantage of using FIR filter for the purpose of decimation is because of its

complexity on circuit design. The FIR filters occupy a larger area on chip because of need

of multipliers to store the coefficients for the filter design. The main disadvantage of FIR

filters is that considerably more computation power in a general purpose processor is

required compared to an IIR filter with similar sharpness or selectivity, especially when

low frequency (relative to the sample rate) cutoffs are needed.

1.4 IIR filters

The IIR filters can also be used for the purpose of decimation and known as recursive

filters. The output of IIR filter depends on past and present values of both input and output

values. IIR filter require less memory and calculations as compare to the similar FIR filter.

4

Limitations

The IIR filters are more costly as compare to that of FIR filter. The IIR filters are more

complex to design, unstable and are non-linear phase response and hence not suitable for

the operation of decimation and sensitivity to quantization errors.

1.5 Objectives:

1. To study CIC filter and implementing it using MATLAB

2. To observe frequency response of CIC filter for various filter orders and sample rate

converters

3. To optimize attenuation in stop band and the drop in pass band by compensation filter

4. Implementation of Cascaded Integrated Comb filter and its real time application of

audio filtering by CIC compensated filter.

1.6 Motivation of thesis:

In many communication and signal processing systems, it is highly desirable to

implement an efficient narrow-band filter that decimate or interpolate the incoming

signals. Fast sampling rate offers several benefits, including the ability to digitize

wideband signals, reduced complexity of anti-alias filters, and lower noise power

spectral density. The decimation filter is a sampling rate conversion system, performs

low-pass filtering as well as down-sampling operation and hence widely used in

speech processing and communication systems application.

In 1981, Eugene Hogenauer invented a new class of economical digital filters for

decimation and interpolation (converting the sampling rate from low to high) called a

Cascaded Integrator Comb (CIC) filter. This filter was composed of an integrator part and

a comb part. No multipliers were required and the storage requirement was reduced when

compared with other implementations of decimation filters. The CIC filter can also be

implemented very efficiently in hardware due to its symmetric structure. Cascaded-

Integrator-Comb (CIC) filter is the simplest decimation filter. A number of cascaded

integrator comb pairs are chosen to meet the design requirements for aliasing or

imaging errors. Although, the CIC filters can implement decimation and interpolation

efficiently in the hardware for a wide range of rate change factors, yet CIC filter

response is lacking in a flat pass-band response and better transition bandwidth.

The CIC filters are an unparalleled class of the digital filters that present a

computationally effective manner of implementing the narrowband low-pass filter for

anti-aliasing. The CIC filter uses only delays and summation units, and it does not

5

require multiplication operations as in an FIR filter. Occasionally, these are referred to as

filters without multipliers. The filter can be implemented by cascading either the

integrator with the comb filter or vice-versa. The low-pass frequency response can be

improved by cascading N number of CIC filter stages. These filters also have a linear

phase response like the FIR filters. The FIR filters can be employed for the

interpolation as well as decimation.

1.7 Organization of dissertation:-

This dissertation consists of six chapters including introduction as follows:

Chapter 1 provides overview of basic digital filters and introduction to CIC filters.

Chapter 2 deals with literature review in which evolution and study of CIC filter is

discussed.

Chapter 3 discuss about the CIC architecture, its frequency response, advantages,

disadvantages and its applications.

Chapter 4 provides the d e s i gn o f d e c i m a t or a n d i n t e r p o l a t o r s us i n g C IC

f i l t e r. Also the compensation techniques for flat passband are discussed.

Chapter 5 deals with the hardware implementation of CIC filters and its real world

signal implementation.

Chapter 6deals with the results and its analysis.

Chapter 7 discuss about its conclusion and future scope.

6

CHAPTER 2

LITERATUTE REVIEW

CIC filters are found in areas of signal processing, communications and etc. for various

applications. The below literature review gives the history and evolution of CIC filters.

Even it’s various forms and the compensation techniques provided by the researches is

discussed.

.

T. Saramaki et al. 7 introduced a new structure for CIC implementation based on 8.

Comb filter in cascade is known to provide an effective first stage for multistage VLSI

implementation of decimators. In this structure tapped interconnections were used instead

of direct cascade. With this structure, the number of comb filters required were reduced

considerably and also the silicon area was reduced for VLSI implementation. Data word

length which is required for internal calculations was also considerably reduced. So a

significant saving was achieved with this structure.

G. J. Dolecek et. al. 6 presented a simple second order sine based CIC. Depending on

the number of stage K, there is only one design parameter which again depends on whether

compensation is narrowband or wideband. It just uses three additions/subtractions to

perform efficient compensation. The method requires very less computations and is less

complex. CIC compensation is convenient in less than 3/5 of total band.

Eghbali et al. 2 have presented the FIR filter structures with multiplierless

implementation. It defines the number of adders needed by the transposed direct structure

as well as polyphase system with decreased complexity The design and realization of FIR

decimation filter structures with sharp transitions are very complicated, sometimes

impractical using single-stage structures. The FIR filter length varies inversely to the width

of the pass band and it becomes complicated for sharp filters. Therefore, realization of the

decimation filter structures with is done with multi-stages. In addition the complexity of

the decimation filter structures are significantly reduced by the introduction of comb

structure in the initial stages.

Hogenauer 4 intended a class of digital filter with only adders and memory elements for

interpolation and decimation to reduce the hardware realization complexity. The filter was

named as Cascaded Integrator-Comb filter since it contains an identical number of

integrators functioning at high sampling rate and comb sections works at the low sampling

7

rate. The CIC filter structures having zero multipliers, comprising only delay elements and

adders, which is an important merit while targeting low power consumption. The number

of CIC sets is selected to satisfy the system prerequisites to overcome the effects of

imaging or aliasing error. The magnitude characteristics of CIC filters is completely

controlled by only two integer parameters and results a restricted range of filter features.

The two control parameters are; decimation/interpolation factor (M) and number of

cascaded integrator-comb sets (K). The aliasing/imaging error in the pass band can be held

within arbitrary bounds by appropriate choice of these parameters in the framework.

Kaiser and Hamming 5 portrayed the filter sharpening method dependent on the

concept of amplitude change function and restricted to symmetric non-recursive filters.

When processing data by filters, it is needed to enhance the magnitude characteristics of

the filter, either by improving the out of-band rejection or by reducing the error in the

passband or both. This sharpening procedure tries to enhance, magnitude characteristics of

a symmetric non-recursive filter by adopting several copies of the similar filter. This

process is called filter sharpening.

G. Molnar et al. 8 proposed a filter called CIC compensator for reduction in droop of

CIC filters. The high order finite impulse response filter based on maximally flat criteria is

presented. The coefficients of compensator were obtained by solving linear equations. If

implemented with double precision arithmetic it allows the compensator design up to 18

coefficients. They give efficient results with wideband system and in case of narrowband

which use high order decimation filters.

.

Kwentus et al. 9 proposed the CIC based programmable multirate decimation filter

structure which enhances the magnitude responses using filter sharpening approaches. This

filter structure permits the initial stage of CIC decimation filter followed by secondstage

filter of fixed coefficient instead of a programmable filter thereby obtaining a considerable

hardware savings when compared to techniques available. It maintains the advantages of

the conventional multiplierless CIC methodology and provides a tangible, PSOCs having

higher data rates using the above structure

8

CHAPTER 3

CASCADED INTEGRATOR COMB FILTER

Cascaded Integrator-Comb (CIC) digital filters are computationally efficient

implementations of narrowband lowpass filters and are often embedded in hardware

implementations of decimation and interpolation in modern communications systems. CIC

filters were introduced to the signal-processing community, by Eugene Hogenauer. In

1981, Eugene Hogenauer invented a new class of economical digital filters for decimation

and interpolation (converting the sampling rate from low to high) called a Cascaded

Integrator Comb (CIC) filter. This filter was composed of an integrator part and a comb

part. No multipliers were required and the storage requirement was reduced when

compared with other implementations of decimation filters. The CIC filter can also be

implemented very efficiently in hardware due to its symmetric structure

3.1 Moving average filter

This is a very inexpensive to realize filters as they do not need multipliers for their

implementation. They can be realized just using delays, adders/ subtractors. All the

weights are set to one.

Fig.3.1: D – point MA filter

The moving average filter is a simple Low Pass FIR (Finite Impulse Response) filter

commonly used for smoothing an array of sampled data/signal. It takes D samples of input

at a time and take the average of those D-samples and produces a single output point. It is a

;#3627408487;

;#3627408487;

;#3627408487;

;#3627408485;(;#55349;;#56411;) ;#3627408486;(;#55349;;#56411;)

Requires D+1 summations

;#3627408485;(;#55349;;#56411;?;#55349;;#56375; 1)

1;#55349;;#56375;

………

.

9

very simple LPF (Low Pass Filter) structure that filters unwanted noisy component from

the intended data.

As the filter length increases ( the parameter D ) the smoothness of the output increases,

whereas the sharp transitions in the data are made increasingly blunt. This implies that this

filter has excellent time domain response but a poor frequency response.

The D-point moving average filters output in the time domain is expressed as:

( ) 1

( ( ) ( ?1) ( ? ) ( ? 1))

Where n is time domain index. The z-domain expression for this moving average filter is:

( )

( ( ) ( ) ( ) ( ) ))

While its z-domain H(z) transfer function is: ( ) ( )

( )

=

(1 )

=

? -n

The MA filter perform three important functions:

1) It takes M input points, computes the average of those D-points and produces a

single output point

2) Due to the computations involved, the filter introduces a definite amount of delay

3) The filter acts as a Low Pass Filter (with poor frequency domain response and a

good time domain response).

The moving average filter is a special case of the regular FIR filter. Both filters have finite

impulse responses and a sequence of scaled 1s are the coefficients of the moving average

filter, while the FIR filter coefficients are designed based on the filter specifications(not

usually a sequence of 1s.)

The moving average of streaming data is computed with a finite sliding window:

Mov avg = ( ) ( ?1) ( ? )

1

N+1 is the length of the filter. This algorithm is a special case of the regular FIR filter

with the coefficients vector, b0, b1, ….., bN .

FIR Output=b0 xn + b1xn?1 +…+ bN xn?N

10

To compute the output, the regular FIR filter multiplies each data sample with a coefficient

from the b0, b1, …, bN vector and adds the result. The moving average filter does not use

any multipliers. The algorithm adds all the data samples and multiplies the result

with 1/ filterLength

3.2 Recursive running – sum filter

Fig.3.2: D-point recursive running sum filter

The current sample x(n) is added and the oldest input sample x(n-D) is subtracted from

the previous output y(n-1). It’s called “recursive” because it has feedback. Each filter

sample is retained and used to compute the next output value. The recursive running sum

filters difference equation is:

( ) 1

( )? ( ? ) ( ?1)

Having a z-domain H(z) transfer function of : H(z) =

�

�

�

�(��) �(��)

Previous average �(��?1)

�(��?�� 1)

1��

………

.

�

–

11

3.3 Digital Integrator

Fig.3.3: Basic Integrator

The integrator circuit is similar to an accumulator which is used to accumulate or store the

sum of the input data. It is a single-pole IIR filter with a filter coefficient factor of one. It

has the low-pass characteristics (infinite gain at DC) with no multipliers required.

The time domain equation is given as: ( ) ( ) ( ?1)

The transfer function of the integrator is shown as:

( )

The output of the integrator is the sum of the present input and the past output as can be

observed from the time domain representation.

The delay element is used to delay the output signal by one clock period and can be

implemented using a memory element. A simple register can be used to achieve the delay.

The transfer function in z-domain representation can be converted into a frequency domain

by substituting z with ( ). The magnitude response of the integrator is given and the

plot showing the magnitude response of the integrator

( )

? (

)

The magnitude response of the integrator shows that the integrator has an infinite gain at

DC (zero frequency) and at multiples of the sampling frequency fs. The integrator has a

minimum value of 0.5 but the frequency of operation that is of interest is at fs. Since the

gain is infinite at DC and at fs, it might cause the integrator to become unstable and there

is every chance that the register used in the delay element could overflow causing data

loss. In order to avoid problems with register overflow, two’s complement coding scheme

is used.

;#3627408487;

;#3627408486;(;#55349;;#56411;) ;#3627408485;(;#55349;;#56411;)

12

3.4 Comb filter:-

Fig.3.4: Basic Comb

A comb filter is used to add delay version of a signal itself. The frequency response of a

comb filter consists of a series of regularly spaced spikes, giving the appearance of a comb.

Comb filter section operates at the low sampling rate, fs / R, where R is the integrate

change factor and the weights are set to 1 and -1 at either end of the filter. This section

consists of N comb stages with a differential delay of M samples per stage. The

differential delay is a filter design parameter used to control the filter’s frequency

response.

The time-domain output may be shown as

? ?

output in the z-domain may be as shown as

?

It may also written as

(1? )

The system function for a single comb stage referenced to the high sampling rate is

( ) 1?

Comb filters find applications in a wide range of practical systems such as in the

rejection of power line harmonics and in the suppression of clutter from fixed objects in

moving-target-indicator (MTI) radars.

� ����

�(��) �(��)

13

3.5 Integrator-Comb Section

Fig.3.5: Basic IC section

An integrator-comb is used to implement the moving average. It produces a simple low-

pass characteristics with no multipliers required. Condensing the delay-line representation

and ignoring the 1/D scaling in fig.3.2, classic form of a 1st-order CIC filter is obtained,

whose cascade structure is shown in fig.3.5. The feedforward portion of the CIC filter is

called the comb section, whose differential delay is M, while the feedback section is

typically called an integrator. The comb stage subtracts a delayed input sample from the

current input sample, and the integrator is simply an accumulator.

The CIC filter’s difference equation is:

( ) ( )? ( ? ) ( ?1)

and its z-domain transfer function is:

1? ?

1? ?1

The filter structures imply, that M weight comb is similar to moving average filter with

weight M-1.Therefore CIC filter has an advantage over moving average that it has only 2

additions compared to 8 in moving averager. Since CIC is originated from the moving

average, magnitude response of both the structures are same.

3.6 Cascaded Integrator Comb filter

A number of integrator-comb sections are cascaded to produce higher order response. A

CIC filter consists of an equal number of stages of ideal integrator filters and comb filters.

Its frequency response may be tuned by selecting the appropriate number of cascaded

integrator and comb filter pairs. The highly symmetric structure of a CIC filter allows

efficient implementation in hardware.

;#3627408487; ;#55349;;#56389;;#55349;;#56384; ;#3627408487;

;#3627408486;(;#55349;;#56411;) ;#3627408485;(;#55349;;#56411;)

14

3.6 Architecture of CIC filter:-

The CIC filter is a class of hardware-efficient linear phase FIR digital filters A CIC filter

consists of an equal number of stages of the ideal integrator filters and the comb filters.

Its frequency response may be tuned by selecting the suitable number of cascaded

integrator and comb filter pairs. The extremely symmetric structure of the CIC

filter authorizes effective implementation in the hardware. . The CIC filters realize

sampling rate decrease (decimation) and sampling rate increase (interpolation)

without using multipliers. However the disadvantage of a CIC filter is that, its pass-band

is not flat, which is disagreeable in many applications. Fortunately, this problem can be

alleviated by using a compensation filter. The CIC decimator would have N cascaded

integrator stages clocked at fs, followed by a change in the rate by a factor R,

followed by N cascaded comb stages consecutively running at fs/R.

Between the two filters sections is a rate change switch. CIC decimation would have N

cascaded integrator stages clocked at fs , followed by a rate change by a factor R,

followed by N cascaded comb stages running at fs/R as shown in figure.

Fig.3.6: CIC Decimator Filter

CIC interpolator would be N cascaded comb stages running at fs/R, followed be a

zero-suffer, followed by N cascaded integrator stages running at fs as shown in figure

Fig.3.7: CIC Interpolator Filter

15

The transfer function for a CIC filter at fs is

( ) ( )

( ) ?

This equation shows that even though a CIC has integrators in it, which by them has an

infinite impulse response, a CIC filter is equivalent to N FIR filters, each having a

rectangular impulse response. Since all of the coefficients of these FIR filters are

unity, and therefore symmetric, a CIC filter has a linear phase response and a constant

group delay. The numerator represents the transfer function of a differentiator and the

denominator indicates the transfer function of an integrator. A very poor magnitude

response of the comb filter is improved by cascading the several identical comb

filters.

3.7 Frequency characteristics of CIC filter:-

CIC filters have a low pass frequency characteristic. The frequency response is evaluated

by

Z =

0??f ??R/2

Where f is the frequency relative to the low sampling rate, fs / R . The cut off

frequency for this filter is fC again relative to the low sample rate. The magnitude

response at the output of the filter can be shown as:

( ) = ( )

(

)

By using the relation sin(x) x for small value of x and some algebra, we can

approximate this function for large value of R as

( ) RM ( )

(

)

0

2N

2N

16

The magnitude response implies that nulls exist at multiples of f ??

?Thus the

difference delay M can be used as a design parameter to control the?

placement of nulls. For CIC decimation filters, the region around every Mth null is

folded into the passband causing aliasing errors; and for CIC interpolation filters,

imaging occurs in the region around these same nulls.

Where M is differential delay, D or R is rate change factor and N is the number of stages.

For practical design problems, the aliasing/imaging errors can be characterized by the

maximum error over all aliasing/imaging bands. For a large class of filter design

problems where fC ??

, lower edge of the first aliasing/imaging band at

fAI ?1??fC

It also implies that DC gain of the filter is a function of the rate change factor.

3.8 1ST order CIC filter response

The time domain impulse response of 1st order (M=1, D =8):

Fig.3.8: Simulation results of the Single-stage CIC filter, time-domain responses when

D = 8

If a unit-impulse-sequence, a unity-valued sample followed by many zero-valued samples,

was applied to the comb stage, the initial positive impulse from the comb filter starts the

17

integrator’s all-ones output. Then, D samples later, the negative impulse from the comb

stage arrive at the integrator to zero all further CIC filter output samples

Fig.3.9: Simulation results of the Magnitude response of a single-stage CIC filter when

D= 8

It is a linear phase low pass filter with sin(Mx)/sin(x) amplitude characteristics. Due to this

response it is also called as sinc filter. CIC filter with transfer function Hc(ejw) exhibit a

comb like response. It has nulls at f=1/M.

Only 2 parameters can be used to modify the magnitude response of comb filter which are

R i.e. filter order and K which is the number of comb filter section. We observe from the

frequency response that firstly, nulls occur at exactly the integral multiple of Fs/M.

Secondly, aliasing bandwidth (bandwidth around nulls) is narrow which is too small for

sufficient suppression of aliasing in whole baseband of signal. Thirdly, the pass band

characteristics of a filter produce droop in pass band called pass band drop which needs to

be compensated for many applications.

As CIC filter shows a poor magnitude characteristics so we improve this by cascade of

number of stages. A CIC filter consists of an equal number of stages of the ideal integrator

filters and the comb filters. Its frequency response may be tuned by selecting the suitable

number of cascaded integrator and comb filter pairs. The extremely symmetric structure of

the CIC filter authorizes effective implementation in hardware.

18

3.9 CIC filter responses for higher orders

The time domain impulse response and magnitude response of CIC filter from 1st to 5th

order:

Fig.3.10: Simulation results of the time-domain responses of the CIC filter when M = 8

(from 1st to 5th orders)

Fig.3.11: Simulation results of the magnitude responses of the CIC filter when M = 8 (from

1st to 5th orders)

19

The multi-stage realization improves the selectivity and the stop-band attenuation of

the overall filter. The selectivity and stop-band attenuation are augmented with the

increasing number of comb filter sections. The filter has multiple nulls with

multiplicity equal to the number of sections. Consequently, the stop-band attenuation in

the null intervals is very high.

The decrease in the magnitude response of pass band is called pass band drop. As we see

as we increase the number of stages, stop band attenuation increases but simultaneously

drop at low frequencies becomes prominent and it creates problem as one is always

interested in lower frequencies. The response with increase in the number of stages of CIC

filter shows that pass band drop got worsened and the stop band got better. It shows that

the multi stage implementation improves stop band and selectivity of filter. Stop band

attenuation in nulls is high as the filter processes multiple nulls whose multiplicity is equal

to number of stages.

3.10 Problem formulation

The simplest multiplier less filter is CIC filter. The CIC filters are multiplication free

filters with limited storage requirements, which make them ideal for the high speed data

converters. Hogenauer presented an FIR structure, which consists of cascaded

Integrator stages working at the higher sampling rate and the same number of comb

stages working at the low sampling rate. CIC filter consists of an equal number of

stages of the ideal integrator filters and the comb filters. A number of cascaded

integrator comb pairs are chosen to meet the design requirements for aliasing or

imaging errors.

The disadvantage of a CIC filter is that, its pass-band is not flat, which is disagreeable in

many applications and the frequency response of CIC filter is fully determined by only

three integer parameters (R, M and N) resulting in a limited range of filter

characteristics. The magnitude response of this filter has a high passband droop. The

main aims of this work to improve the magnitude response of CIC filters and also

solve the passband droop problem. The droop can be reduced by modifying the

original CIC structure or by connecting an additional filter called CIC compensator in

cascade with the CIC decimator. The former approach is based on a technique called

sharpening. In recent years, several methods for the design of CIC compensators have

been developed and now compensation is combined with a sharpening technique.

20

3.11 Advantages & Disadvantages of CIC filter:-

There are some advantages of the CIC filters:-

1. No multipliers are required

2. No storage is required for filter coefficients

3. Intermediate storage is reduced by integrating at high sampling rate and comb

filtering at low sampling rate

4. Little external control or complicated local timing is required

The same filter design can be used for a wide range of rate change factor R with the

addition of a scaling circuit and minimal change to the filter timing.

3.12 Applications

• Channelization functions in a digital radio or MODEM

• Part of the digital up-conversion signal processing chain in a transmitter

• Any filter structure that is required to efficiently effect a large sample rate change

• The application for CIC filters seems to be in areas where high sampling rates make

multipliers an uneconomical choice and areas where large rate change factors would

require large amount of coefficient storage or fast impulse response generation.

21

CHAPTER 4

SAMPLE RATE CONVERTERS

Multi-rate processing and sample rate conversion, or interpolation and decimation are a

clever Digital Signal Processing (DSP) techniques that broadband and wireless design

engineers can employ during the system design process. Using these techniques, design

engineers can gain an added degree of freedom that could improve the overall performance

of a system architecture.

Sample rate conversion, on the other hand, is employed when resampling a signal at a

lower rate in order to allow it to pass through a channel with limited bandwidth.

Additionally, this technique can be employed to develop highly accurate Delta-Sigma

Analog-to-Digital Converters (ADCs) with a high modulation rate at the front end

followed by a decimator to reduce sampling rate, thus providing converted samples at or

near the Nyquist rate. There are three types of sampling rate conversion. Decimation is

process of reducing the sampling rate i.e. when the desired sampling rate is less than the

existing sampling rate and when the desired sampling rate is more than the existing one the

process known as interpolation plays its role. These processes need to be used with care

they give rise to aliasing and imaging. These include down conversion or decimation by a

factor R; up conversion by a factor I; and sampling rate conversion by a ratio of R and I.

4.1 Types of decimation filter

The advantages and disadvantages of various decimation filters are explained below.

Generally there are three types of filters used for the operation of decimation as explained

below:

FIR filters

Advantages

FIR filters can be used for the process of decimation and are also known as non-recursive

filters. The output of FIR filter depends upon past and present values of input. The FIR

Decimation block resamples the discrete-time input at a rate K times slower than the input

sample rate. The block down samples the filtered data to a lower rate by discarding (K-1)

consecutive samples following every sample retained. The design of FIR filter is based on

the often added requirement that the phase response be linear. FIR filter is not based on

any feedback path and can easily be designed to be linear phase by making the coefficient

22

sequence symmetric i.e. equal delay at all frequencies. This property is sometimes desired

for phase-sensitive applications.

Disadvantages

The disadvantage of using FIR filter for the purpose of decimation is because of its

complexity on circuit design. The FIR filters occupy a larger area on chip because of need

of multipliers to store the coefficients for the filter design. The main disadvantage of FIR

filters is that considerably more computation power in a general purpose processor is

required compared to an IIR filter with similar sharpness or selectivity, especially when

low frequency (relative to the sample rate) cutoffs are needed.

IIR filters

Advantages

The IIR filters can also be used for the purpose of decimation and known as recursive

filters. The output of IIR filter depends on past and present values of both input and output

values. IIR filter require less memory and calculations as compare to the similar FIR filter.

Disadvantages

The IIR filters are more costly as compare to that of FIR filter. The IIR filters are more

complex to design, unstable and are non-linear phase response and hence not suitable for

the operation of decimation and sensitivity to quantization errors.

Comb filters

The Comb filters can be stated as an optimized FIR filters used for the purpose of

decimation. The coefficients of FIR filters are optimized or set to unity. The comb filters

introduces distortion of the incoming signal due to high passband droop and low stop-band

attenuation in its frequency response. These filters require no multipliers and use limited

storage thereby leading to more economical hardware implementations. They are

designated Cascaded Integrator-Comb (CIC) filters because their structure consists of an

integrator section operating at the high sampling rate and a comb section operating at the

low sampling rate. Using CIC filters, the amount of passband aliasing or imaging error can

be brought within prescribed bounds by increasing the number of stages in the filter.

However, the width of the passband and the frequency characteristics outside the passband

are severely limited.

Advantages of using Comb filters as decimation filter.

1. The Comb filters a class of optimized FIR filters are used for the purpose of

decimation filters because of multiplier less design in hardware.

23

2. The coefficients of comb filters are set to unity to eliminate the need of multipliers

from the design.

3. The filter requires only additions and subtractions for their implementation and

requires simple implementations.

The main advantage of comb filters is to perform decimation and interpolation without

multiplying operation. This is of great advantage when we operate at high frequencies.

While considering implementation of these filters we can expect register growth since the

integrator is having unity feedback coefficient. This can be overcome by using two’s

compliment arithmetic and using range of number system more than the maximum

expected magnitude.

4.2 CIC Decimator

Fig.4.1: CIC Decimator

Downsampling by a factor R is a process where every Rth sample is retained while the (R-

1) samples in between are discarded. The output sample rate hence decreases by a factor of

R. Decimation is a process where anti-aliasing filtering precedes the downsampling

process. The CIC decimator is obtained by interchanging the order of the comb and the

integrator sections in the CIC filter structure, such that the comb section comes first,

followed by the downsampler. Interchanging the comb and integrator section does not

affect the functioning of the filter as it is linear. Below fig depicts the CIC decimator

structure.

24

The integrator section consists of N ideal integrator stages operating at the high sampling

rate fs. Each stage is implemented as a one-pole filter with a unity feedback coef- ficient.

The transfer functions for a single integrator is

( ) 1

1?

The comb section operates at the low sampling rate fs / R where R is the integer rate change

factor. This section con- sists of comb stages with a differential delay of M samples per

stage. The differential delay is a filter design parameter used to control the filter’s

frequency response. M is restricted to be either 1 or 2. The transfer function for a single

comb stage, referenced to the high input sample rate is

( ) 1?

There is a rate change switch between the two filter sections. The decimator subsamples

the output of the last integrator stage, reducing the sample rate from fs to fs /R. The system

transfer function for the composite CIC filter, referenced to the high sampling rate, is

( ) ( )

( ) ?

4.3 CIC Interpolator

Fig.4.2: CIC Interpolator

Upsampling by a factor R is the process of inserting (R-1) zerovalued samples between

original samples in order to increase the sampling rate. The output sample rate increases by

a factor R. Upsampling by R adds to the original signal (R-1) undesired spectral images

which are centered at multiples of the original sampling rate. CIC filters are used as anti-

imaging filters for interpolated signals in order to remove the unwanted spectral

images .The comb section precedes the integrator in a CIC interpolator. Below fig depicts

the CIC interpolator structure

25

4.4 Noble identities

Use of the Noble identity allows reduction of number of multiplications and additions,

since filtering is performed at a lower rate.

4.5 Drawbacks in CIC filters frequency response

Because their frequency-magnitude-response envelopes are sin(x)/x-like, CIC filters are

typically either followed or preceded by higher performance linear-phase lowpass tapped-

delay-line FIR filters whose tasks are to compensate for the CIC filter’s non-flat passband.

That cascaded-filter architecture has valuable benefits. For example, with decimation, you

can greatly reduce computational complexity of narrowband lowpass filtering compared

with if you’d used a single lowpass finite impulse response (FIR) filter. In addition, the

follow-on FIR filter operates at reduced clock rates minimizing power consumption in

high-speed hardware applications.

In typical decimation/interpolation filtering applications we want reasonably flat passband

and narrow transition-region filter performance. These desirable properties are not

provided by CIC filters alone, with their drooping passband gains and wide transition

regions. The compensation FIR filter’s frequency magnitude response is ideally an inverted

version of the CIC filter passband response. If either the passband bandwidth or CIC filter

order increases the correction becomes greater, requiring more compensation FIR filter

taps.

26

4.6 Compensation techniques

? Double sharpened CIC decimation filter: generalized comb filter as first stage,

sharpened comb filter as second and third stage.

? Ideal CIC compensator: compensator having inverse amplitude response of

decimator filter is connected at the output of CIC decimator.

Ideal CIC compensator

The CIC Compensation Decimator block uses an FIR polyphase decimator as the

compensation filter. CIC compensation decimators are multirate FIR filters that can be

cascaded with CIC decimators to mitigate the drawbacks of the CIC filters.

CIC decimation filters are used in areas that require high decimation. These filters are

popular in ASICs and FPGAs, since they do not have any multipliers. CIC filters have two

drawbacks:

? CIC filters have a magnitude response that causes a droop in the passband region. This

magnitude response of a CIC filter is:

abs sin

(

)

(

)

o M — Differential delay

o n — Number of stages

o ? — Normalized angular frequency

? CIC filters have a wide transition region.

The compensation decimator filters have an inverse passband response to correct for the

CIC droop, and they have a narrow transition width.

The response of a CIC filter is given by

(w) =

(

)

(

)

N

n

27

After decimation, the CIC response has the form:

(w) =

(

)

(

)

(w) = RD

(

)

(

) for w ? ;

where ?p is the passband frequency of the CIC compensation filter.

N

N

28

CHAPTER 5

HARDWARE IMPLEMENTATION

Multiplierless Finite Impulse Response (FIR) filters are very attractive in VLSI (Very

Large-Scale Integration) implementation. Most of the hardware complexity is due to

multipliers, as filters require large number of multiplication, leading to excessive area,

delay and power consumption even if implemented in a full-custom integrated circuits.

Implementation of systems with multiplications may be simplified by using only a small

number of shift and add operations.

The recent advancement in the VLSI technology particularly in FPGA as made possible,

the realization of advanced Digital Signal Processing algorithm in high frequency domain.

With this development a single chip solution is possible for complex DSP based

applications like, ADC, Decimation and Interpolation in the communication system.

Digital implementation couples with signal processing algorithms greatly enhance the

system performance, reduced the cost and increase the reliability of the system. The

ZedBoard enables hardware and software developers to create or evaluate Zynq™-7000

All Programmable SoC designs. The expandability features of this evaluation and

development platform make it ideal for rapid prototyping and proof-of-concept

development. The ZedBoard includes Xilinx XADC, FMC (FPGA Mezzanine Card), and

Digilent Pmod™ compatible expansion headers as well as many common features used in

system design. ZedBoard enables embedded computing capability by using DDR3

memory, Flash memory, gigabit Ethernet, general purpose I/O, and UART technologies.

5.1 Zedboard

Fig.5.2: Zedboard

29

The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing

performance, power, and ease of use typically associated with ASIC and ASSPs. The range

of devices in the Zynq-7000 family allows designers to target cost-sensitive as well as

high-performance applications from a single platform using industry-standard tools. While

each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary

between the devices.

The Zynq-7000 architecture enables implementation of custom logic in the PL and custom

software in the PS. It allows for the realization of unique and differentiated system

functions. The integration of the PS with the PL allows levels of performance that two-chip

solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth,

latency,and power budgets. The PS and the PL are on separate power domains, enabling

the user of these devices to power down the PL for power management if required. The

processors in the PS always boot first, allowing a software centric approach for PL

configuration. PL configuration is managed by software running on the CPU, so it boots

similar to an ASSP.

Fig.5.3: Basic Architecture of Zedboard

For hardware implementation, the following steps are performed:

1. Set up your Zynq hardware and tools.

2. Partition your design for hardware and software implementation.

3. Generate an HDL IP core.

4. Integrate the IP core into a Xilinx Vivado project and program the Zynq hardware.

5. Generate a software interface model.

30

6. Generate C code from the software interface model and run it on the ARM Cortex-

A9 processor.

7. Tune parameters and capture results from the Zynq hardware using External Mode.

5.2 Procedural flow:

1. Development of CIC filter using model based design.

2. Compile and run the model.

3. Generate the HDL code for filter and its testbench

4. Export the generated HDL model into xilinx vivado tools(modelsim) and simulate

for results. Verify these results against the Matlab results

5. For Zynq hardware-software co-design workflow decide which parts of the design

to implement on the programmable logic, and which parts to run on the ARM

processor.

6. Group all the blocks that are to be implemented on programmable logic into an

atomic subsystem. This atomic subsystem is the boundary of the hardware-software

partition. All the blocks inside this subsystem will be implemented on

programmable logic, and all the blocks outside this subsystem will run on the ARM

processor.

7. Generate the ipcore and map each port of DUT to one of the IP core target

interfaces.

? AXI4 – for high performance memory mapped requirements.

? AXI4-Lite – for simple, low throughput memory mapped communication.

For example, to and from control and status registers.

? AXI4-Stream – for high speed streaming of data

8. For the AXI4-Lite interface, HDL Coder generates AXI interface accessible

registers for them.

9. Insert the generated IP core into a embedded system reference design, generate an

FPGA bitstream, and download the bitstream to the Zynq hardware.

10. The reference design is a predefined Xilinx Vivado project. It contains all the

elements the Xilinx software needs to deploy the design to the Zynq platform,

except for the custom IP core and embedded software that gets generated.

11. After the bitstream is generated, download the FPGA bitstream onto the SD card on

the Zynq board, so that the design will be automatically reloaded when the Zynq

board is power cycled.

31

12. After the generation of IP core and inserting it into the Vivado reference design, a

software interface model can be generated optionally.

13. The software interface model contains the part of the design that runs in software. It

includes all the blocks outside of the HDL subsystem, and replaces the HDL

subsystem with AXI driver blocks. The generated embedded software includes AXI

driver code, generated from the AXI driver blocks, that controls the HDL IP core.

In the generated software interface model, the subsystem is replaced with the AXI

driver blocks which generate the interface logic between the ARM processor and

FPGA

5.3 Verification methods

SOFTWARE-IN-LOOP

Refers to the kind of testing done to validate the behavior of the auto generated code used

in the controller. The embedded software is tested within a simulated environment model

but without any hardware. SIL also allows to verify the code coverage.

PROCESSOR-IN-LOOP

Refers to the kind of testing done to validate the referenced model by generating

production code using the model reference target. The code is cross-compiled for and

executed on a target processor or an equivalent instruction set simulator. PIL level of

testing can reveal faults that are caused by the target compiler or by the processor

architecture.

5.4 Implementation of real world signal

Receive audio input through Zedboard board's line input, process it on the FPGA and

transmit the processed audio to a speaker. It uses an audio codec to interface to the

peripherals and to convert analog to digital signals and vice-versa. The Audio Codec IPs

are used to configure the audio codec and for transferring audio data between Zynq Soc

and audio codec. The Filter IP is used for audio processing. ARM processor is used to

control the type of filter to be used i.e. low pass, band pass or high pass. The filtered audio

output can be heard by plugging earphones or speakers to HPH OUT jack on the Zynq

board.

32

Fig.5.4: Block diagram for audio filtering

Steps involved

1. Model a system with CIC filter.

2. Customize the model for zynq board.

3. Generate HDL IP core with AXI4-Stream interface

4. Integrate IP into AXI4-Stream audio compatible reference design.

5. Generate ARM executable to tune parameters on the FPGA fabric.

An audio signal with a maximum frequency of 20KHz is given as input externally to the

Zedboard in which code is already dumped. The filter can be enabled/disable externally

via dip switches. When the filter is enabled i.e., CIC filter, only a band of frequencies 0-3

KHz is passed due to its low-pass characteristics and when the filter is disabled all

frequencies all allowed i.e., acts all pass filter. Based upon the application the cutoff

frequency of the filter can be altered and implemented similarly in hardware.

The filter performance can be analyzed using spectrogram available in Simulink. The

following figures 5.5 and 5.6 shows the spectral analysis of filtered audio signal when CIC

filter is disabled ( all pass filter) and enabled respectively.

33

Fig.5.5: Spectrogram of All pass filter

Fig.5.6: Spectrogram of Low pass filter(CIC)

34

5.5 Flowchart

Model based

Algorithm and System

Design

HDL IP Core

Generation

Embedded System Tool

Integration

FPGA Bitstream

ZYNQ Platform

Software Interface Model

Generation

SW Build

External Mode

35

CHAPTER 6

RESULTS AND ANALYSIS

The programming tool Simulink, part of MATLAB has been used in order to determine the

required outputs. The CIC filter and an application of it have been implemented using Simulink

and the respective outputs have been analyzed. Initially frequency response of 1st order CIC filter

has been observed and then with increased number of stages. Further the responses of CIC

decimator and interpolator haven observed. Finally CIC compensated filter and basic FIR filter

have been compared considering various factors.

The scope represents the frequency response of CIC filters for discrete impulse as input, with x

axis as frequency in hertz and y axis as magnitude I db. The spectrogram shows the time

distribution of the signal with respect to various frequency bands, the variation from low

frequency to high frequency components subtly represented using variation in colors.

1. Considering discrete impulse as input the following observations have been made,

Fig.6.1: Simulation results of the MA filter for D=8

36

Fig.6.2: Simulation results of the CIC filter for D=8

The filter structures implies that D weight comb is similar to moving average filter with weight

D-1.Therefore CIC filter has an advantage over moving average that it has only 2 additions

compared to 8 in moving averager. Since CIC is originated from the moving averager we have

magnitude response of both the structures the same.

Integrator + D-weight Comb = (D-1) Weight MA

2. For the same input, the time domain plot and frequency response for the 1st order CIC

filter is observed as

Fig.6.3: The time domain impulse response of 1st order (N=1, D=8)

37

Fig.6.4: Simulation results of the Magnitude response of a single-stage CIC filter when D= 8

Analysis:

? It is a linear phase low pass filter with sin(Mx)/sin(x) amplitude characteristics. Due to

this response it is also called as sinc filter. CIC filter with transfer function Hc(ejw) exhibit

a comb like response. It has nulls at f=1/M.

? Secondly, aliasing bandwidth (bandwidth around nulls) is narrow which is too small for

sufficient suppression of aliasing in whole baseband of signal.

? Thirdly, the pass band characteristics of a filter produce droop in pass band called pass

band drop which needs to be compensated for many applications.

As CIC filter shows a poor magnitude characteristics so we improve this by cascade of number

of stages. A CIC filter consists of an equal number of stages of the ideal integrator filters and the

comb filters. Its frequency response may be tuned by selecting the suitable number of cascaded

integrator and comb filter pairs. The extremely symmetric structure of the CIC filter authorizes

effective implementation in hardware.

38

3. With increase in the number of stages of CIC filter, the following observations have been

made,

Fig.6.5: Simulation results of the time-domain responses of the CIC filter when D = 8 (from 1st

to 5th orders)

Fig.6.6: Simulation results of the magnitude responses of the CIC filter when M = 8 (from 1st to

5th orders

39

Fig.6.7: Magnitude response of 1st and 3rd order CIC filters

As the order of CIC filter increases the attenuation band decreases by some factor.

Comparison of attenuation bands

Table 6.1 Comparison of attenuation bands of CIC filter

The response with increase in the number of stages of CIC filter shows that pass band drop got

worsened and the stop band got better The decrease in the magnitude response of pass band is

called pass band drop.

No. of sections Rate change factor Cut-off(-3dB)

(Hz)

Attenuation

band drop (dB)

1 16 2.783e+06 -13.5

3 16 1.66e+06 -39.44

1 8 5.518e+06 -12.8

3 8 3.271e+06 -38.44

1 4 6.689e+06 -11.31

3 4 4.152e+06 -33.91

40

Increase in the number of stages, stop band attenuation increases but simultaneously drop at low

frequencies becomes prominent and it creates problem as we are always interested in lower

frequencies.

It shows that the multi stage implementation improves stop band and selectivity of filter. Stop

band attenuation in nulls is high as the filter processes multiple nulls whose multiplicity is equal

to number of stages.

4. Changing the parameters differential delay(M), number of stages(N), and rate change factor,

the outputs of CIC sample rate converters can be observed as

Fig.6.8: Simulation results of the CIC decimator with R=8, M=1and N=1

41

Fig.6.9: Simulation results of the CIC decimator with R=8,M=1 and N=6

42

Fig.6.10: Simulation results of the CIC decimator with R=8, M=1,2,4 and N=6

The imaging or aliasing occur in the regions around the nulls. More rejection in stop band results

in smaller spectral images or aliasing. Furthermore, if the number of stages, K is increased it will

result in an undesired increase of pass band “droop” and an undesired increase of net gain which

also are dependent of the delay in combs, M . Now, let RD=M where R is rate change and a

differential delay, D. The differential delay can be used to set the null placements.

An increase of differential delay will cause an even faster pass band “droop” but results in a

moderate increase of the stop band rejection which may not payoff. One important thing is that

the relative bandwidth of the signal determines when it is profitable to use the CIC filter. Clearly,

if the bandwidth is small it will result in a relative flat pass band, high rejection of imaging or

aliasing components.

43

Fig.6.11: Simulation results of the CIC interpolator for I=8,M=1 and N=1

Fig.6.12: Simulation results of the CIC interpolator for I=16,M=1 and N=1

44

Fig.6.13: Simulation results of the CIC interpolator for I=16, M=1 and N=3

45

5. The outputs of CIC compensator filter having an inverse passband response to correct for the

CIC droop, have been observed as

Fig.6.14: Simulation results of CIC compensated filter

Fig.6.15: Simulation results of FIR filter

46

Comparison between ideal CIC compensated filter and FIR filter

Specifications: Fs=100MHz, Passband=25MHz, Stopband=30MHz, 3-dB= 27.3681 dB

For Compensated CIC : R=4; N=4; M=1

CIC compensation:

Decimation factor D=2 D=4 D=8 D=16

Polyphase length 31 16 8 4

Filter length 62 62 62 62

No. of multipliers 62 62 62 62

No. of adders 61 61 61 61

Multiplications per

input sample

31 15.5 7.75 3.875

Additions per input

sample

30.5 15.25 7.6255 3.8125

Table 6.2 Factors influencing CIC compensated filter

FIR filter:

Decimation factor D=2 D=4 D=8

Polyphase length 26 13 7

Filter length 51 51 51

No. of multipliers 51 51 51

No. of adders 50 50 50

Multiplications per

input sample

25.5 12.75 6.375

Additions per input

sample

25.5 12.5 6.25

Table 6.3 Factors influencing FIR filter

47

6. In order to implement CIC filter in hardware, its response is verified in Modelsim as

below:

Fig.6.16: The time domain plots of CIC filter 1st,2nd and 3rd order

Fig.6.17: Verification by Xilinx Vivado tool(Modelsim)

48

CHAPTER 7

CONCLUSION AND FUTURE SCOPE

7.1 Conclusion

The CIC filter has great properties such as no multipliers are required and variable interpolation-

or decimation factor for the same compensation filter. It suffers of a droop in passband which

may set demands on the required compensation filter. However, it turned out that the CIC filter is

best suitable for narrowband signals with higher interpolation- or decimation factors, due the

extra taps needed for the compensation filter.

Decimation of a signal at high frequency using FIR or IIR structures is very complex since it

needs a lot of multiplications and hence system cost is increased. In CIC filter as the number of

stages increases its stop band attenuation improves but pass band droop increases. In many

applications monotonically decreasing pass band droop has to be compensated. CIC filters are

very economic, computationally efficient and simple to implement in comparison with FIR or

IIR for large rate change due to lack of multipliers. One of the difficulties in using CIC filters is

accommodating large data word growth, particularly when implementing integrators in

multistage CIC filters. Thus the CIC filter proves to be more efficient; it reduces power

consumption and thus reduces implementation cost.

7.2 Future scope

Since their inception, CIC filters have become an important building block for Digital Signal

Processing systems. They have found a particular niche in digital transmitters and receivers.

They are currently used in highly integrated chips from Intersil, Graychip, Analog devices, as

well as other manufacturers and custom designs. In areas like communications ,signal and audio

processing CIC filters play a prominent role where high data rate conversions are required.

49

REFERENCES

1. Ramesh Bhakthavatchalu, Karthika.V.S, Lekshmi Ramesh and Budhota Aamani, “Design

of optimized CIC Decimator and Interpolator in FPGA”,proc. IEEE 2013.

2. Athira Shaji and Jayaraj V.S,” FPGA Implementation of an Efficient Cascaded Integrator

Comb filter for Narrow and Wideband Designs”,proc. IEEE 2103.

3. Sneha Raj and Athira Shaji, “Design and Implementation of Reconfigurable Digital Filter

Bank for Hearing Aid”, 2016 International Conference on Engineering Technological

Trends.

4. 2 E. B. Hogenauer, ;An Economical Class of Digital Filters for Decimation and

Interpolation;, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.

ASSP-29, pp. 155-162, April 1981.

5. Kaiser, J. F., and Hamming, R. W., “Sharpening the response of a symmetric nonrecursive

filters,” IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. 25, No. 3,

pp. 415–422, 1977.

6. G. J. Dolecek and S. K. Mitra. “Simple method for compensation of CIC decimation

filter,” in Electron. Lett., vol. 44, no. 19, Sept.2008.

7. Saramaki and T. Ritoniemi, “A modified comb filter structure for decimation,”Proc. IEEE

Int. Symp. on Circuits and Syst., vol. 4, pp.2353–2356, June 1997.

8. G. Molnar and M. Vucic, “Closed-Form Design of CIC Compensators Based

onMaximally Flat Error Criterion,” in IEEE Trans. on Circuits and Syst.—II: Express

briefs , vol. 58, no. 12, pp. 926-930,Dec. 2011.

9. A. Kwentus, Z. Jiang. And A. Willson, “Appliation of filter sharpenins to cascaded

integrated com decimation filters,”in IEEE Trans. Signal Process, vol.45, no. 2, pp.457-

467, Feb 1997.